The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more particularly to an improvement of a pattern formed on a wafer and a method for forming the pattern.
To prepare a mask for use in a process of forming an integrated circuit, in general, a diagram depicted at 1000 to 5000 magnification of a circuit is first prepared. The circuit diagram is converted by a CAD system to data for driving a pattern generator or electron beam exposure system. The pattern generator or electron beam exposure system forms a reticle (enlargement mask) 4 to 10 times enlarged from an actual size.
Generally, a pattern for one or several chips of an integrated circuit is depicted on a reticle. By means of a photo-repeater, the pattern on the reticle is reduced and a number of chip patterns are formed on a hard blank (or photographic plate) to obtain a master mask of an actual size. A master mask can be formed directly by an electron beam exposure system without a photo-repeater.
In recent years, as the integration density of an integrated circuit has been greatly increased and a projection aligner of non-contact type has been developed, a master mask of high accuracy is directly used in a production line, or a wafer is exposed via a reticle by a shot-by-shot exposure by means of a wafer stepper and a projection aligner.
A step and repeat system is one of the typical shot-by-shot exposure systems. In this system, a wafer is vacuum-fixed to an X-Y stage which can be moved two-dimensionally, and the wafer is exposed every time it is transferred by a fixed distance. Although the throughput of this system is lower than that of the full wafer exposure system, a pattern having high resolution is obtained by easy control, since a central portion of the lens used in the step and repeat system has less distortion. In addition, since patterns formed in different steps can be placed one on another, positioning with high accuracy can be achieved.
Both in the step and repeat system and the full wafer exposure system, when a chip pattern is transferred to a wafer, a peripheral portion the pattern may be displaced from the wafer, that is, outline imperfect chips are formed. According to the conventional manufacturing art, to form a pattern on all the portion of a wafer in the same manufacturing conditions, the wafer is exposed at a critical level with the same pattern both in a central portion and a peripheral portion of the wafer.
However, it is difficult to form, particularly, chips of a sub-half micron pattern in the peripheral portion of the wafer in the same design rule pattern as used in the central portion. The reasons for the difficulty are: the depth of focus is inevitably narrow when a fine pattern is projected; the focus in a region near the central portion is also applied to the peripheral portion of the wafer, since an area sufficient for focus measurement cannot be ensured in the peripheral portion; and the wafer is less flat in the peripheral portion than in the central portion.
Further, if a pattern is out of focus, the pattern may be removed in the steps subsequent to the pattern forming, generating foreign matter and lowering the manufacturing yield. More specifically, if foreign matter is adhered to a wafer, it may function as a mask in dry etching or ion implantation, thus forming etching remainder or a conductive inverted layer immediately under the foreign matter. Alternatively, atoms constituting the foreign matter may diffuse into the substrate or lower the adhesion strength of a deposited film.
Of all the external defects generated in the wafer process, defects, which may result from foreign matter adhered to the wafers or masks, are considered to be about 70%. Although outline imperfect chips are not the only cause of all of the external defects, they can be a potential source of defects.